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______________________________________________________________________________________ 11
Single-Port, 40W, IEEE 802.3af/802.3at PSE
Controller with Integrated MOSFET
  Pin Description
  Pin Configuration
26
27
25
24
10
9
11
12
1    2
OUTP
4    5    6    7
20
21
19
17   16   15
OUT
OUT
V
EE_DIG
I.C.
I.C.
I.C.
MAX5971A
3
18
28
8
N.C.
I.C.
N.C.
23
13   LEGACY
DET
22
14
EN
*EXPOSED PAD, CONNECT TO AGND.
*EP
N.C.
THIN QFN
TOP VIEW
+
PIN
NAME
FUNCTION
1, 2, 3
V
EE
Analog Low-Side Supply Input. Bypass with an external 100V, 47FF capacitor in parallel with a
100V, 0.1FF ceramic capacitance between AGND and V
EE
.
4
ILIM1
Class 5 Current-Limit Digital Adjust 1. Referenced to V
EE
. ILIM1 is internally pulled up to the digital
supply. Use ILIM1 with ILIM2 to enable Class 5 operation and to adjust the Class 5 current-limit
value. See the Electrical Characteristics table and Table 3 in the Class 5 PD Classification section
for details.
5
ILIM2
Class 5 Current-Limit Digital Adjust 2. Referenced to V
EE
. ILIM2 is internally pulled up to the digital
supply. Use ILIM2 with ILIM1 to enable Class 5 operation and to adjust the Class 5 current-limit
value. See the Electrical Characteristics table and Table 3 in the Class 5 PD Classification section
for details.
6
PWMEN
PWM Control Logic Input. Referenced to V
EE
. PWMEN is internally pulled up to the digital sup-
ply. Leave unconnected to enable the internal PWM to drive the LED pin. Force low to disable the
internal PWM.
7
MIDSPAN
Detection Collision Avoidance Logic Input. Referenced to V
EE
. MIDSPAN is internally pulled up
to the digital supply. Leave unconnected to activate the detection collision avoidance circuitry
for midspan PSE systems. Force low to disable this function for an end-point PSE system. The
MIDSPAN logic level latches after the device is powered up or after a reset condition.
811, 15
I.C.
Internally Connected. Connect I.C. to V
EE
.
12
V
EE_DIG
Digital Low-Side Supply Input. Connect to V
EE
 externally.
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